? semiconductor components industries, llc, 2013 october, 2013 ? rev. 0 1 publication order number: NCP81146/d NCP81146 vr12.5 compatible synchronous buck mosfet drivers the NCP81146 is a high performance dual mosfet gate driver optimized to drive the gates of both high ? side and low ? side power mosfets in a synchronous buck converter. it can drive up to 3 nf load with a 25 ns propagation delay and 20 ns transition time. adaptive anti ? cross ? conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. bidirectional en pin can provide a fault signal to controller when the gate driver fault detect under ovp, uvlo occur. also, an under ? voltage lockout function guarantees the outputs are low when supply voltage is low. features ? faster rise and fall times ? adaptive anti ? cross ? conduction circuit ? integrated bootstrap diode ? pre ov function ? zcd detect ? floating top driver accommodates boost voltages of up to 35 v ? output disable control turns off both mosfets ? under ? voltage lockout ? power saving operation under light load conditions ? direct interface to ncp6151 and other compatible pwm controllers ? thermally enhanced package ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? power solutions for desktop systems device package shipping ? ordering information NCP81146mntbg dfn8 (pb ? free) 3000 / t ape & reel http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. dfn8 mn suffix case 506aa marking diagram a4 = specific device code m = date code = pb ? free device a4m 1 1
NCP81146 http://onsemi.com 2 figure 1. pin diagram drvh sw gnd drvl bst pwm en vcc 1 flag (top view) 9 bst pwm logic drvh sw anti ? cross conduction vcc drvl vcc en fault uvlo pre ? ov zcd detection figure 2. block diagram table 1. pin descriptions pin no. symbol description 1 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2 pwm control input. the pwm signal has three distinctive states: low = low side fet enabled, mid = diode emulation enabled, high = high side fet enabled. 3 en logic input. a logic high to enable the part and a logic low to disable the part. 4 vcc power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node (qfn flag). 7 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 8 drvh high side gate drive output. connect to the gate of high side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to ground plane.
NCP81146 http://onsemi.com 3 figure 3. application circuit vreg_sw1_hg vccp tp3 vreg_sw1_out vreg_sw1_lg tp6 tp7 tp8 tp4 tp1 tp2 tp5 ntmfs4851n ntmfs4851n q9 q10 ntmfs4821n q1 NCP81146 bst pwm en vcc hg sw gnd lg pad dron pwm csn11 csp11 c1 c2 c3 ce9 l r3 c6 r164 12v_power r1 r143 c4 0.027uf 0.0 1.02 c5 1uf r142 0.0 0.0 2.2 2700pf 235nh 4.7uf 4.7uf 4.7uf 390uf + jp13_etch jp14_etch table 2. absolute maximum ratings pin symbol pin name v max v min vcc main supply voltage input 15 v ? 0.3 v bst bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 15 v wrt/ sw ? 0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v 50 ns ? 5 v ? 10 v (200 ns) drvh high side driver output bst+0.3 v ? 0.3 v wrt/sw ? 2 v (<200 ns) wrt/sw drvl low side driver output vcc+0.3 v ? 0.3 v dc ? 5 v (<200 ns) pwm drvh and drvl control input 6.5 v ? 0.3 v en enable pin 6.5 v ? 0.3 v gnd ground 0 v 0 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. thermal information (all signals referenced to agnd unless noted otherwise) symbol parameter value unit r ja thermal characteristic (note 1) 74 c/w t j operating junction temperature range (note 2) ? 40 to +150 c t a operating ambient temperature range ? 40 to +125 c t stg maximum storage temperature range ? 55 to +150 c msl moisture sensitivity level 1 * the maximum package power dissipation must be observed. 1. i in 2 cu, 1 oz thickness. 2. operation at ? 40 c to ? 10 c guaranteed by design, not production tested.
NCP81146 http://onsemi.com 4 table 4. electrical characteristics ( unless otherwise stated: ? 40 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst ? swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter test conditions min. typ. max. units supply voltage vcc operation voltage 4.5 13.2 v power on reset threshold 2.75 3.2 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv output overvoltage trip threshold at startup power startup time, vcc > por 2.1 2.25 2.4 v supply current normal mode icc + ibst, en = 5 v, pwm = osc, fsw = 100 khz, cload = 3 nf for drvh, 3 nf for drvl 10 ma standby current icc + ibst, en = gnd 0.5 1.4 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 2.0 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 2.0 ma bootstrap diode forward v oltage v cc = 12 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high 3.4 v pwm mid ? state 1.3 2.7 v pwm input low 0.7 v zcd blanking timer 250 ns high side driver (vcc = 12 v) output impedance, sourcing current vbst ? vsw = 12 v 1.9 3.0 output impedance, sinking current vbst ? vsw = 12 v 1.0 1.7 drvh rise time tr drvh v vcc = 12 v, 3 nf load, vbst ? vsw = 12 v 16 30 ns drvh fall time tf drvh v vcc = 12 v, 3 nf load, vbst ? vsw = 12 v 11 25 ns drvh turn ? off propagation delay tpdl drvh c load = 3 nf 8.0 30 ns drvh turn ? on propagation delay tpdh drvh c load = 3 nf 30 ns sw pull down resistance sw to pgnd 45 k drvh pull down resistance drvh to sw, bst ? sw = 0 v 45 k high side driver (vcc = 5 v) output impedance, sourcing current vbst ? vsw = 5 v 2.5 output impedance, sinking current vbst ? vsw = 5 v 1.6 drvh rise time tr drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 30 ns drvh fall time tf drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 27 ns drvh turn ? off propagation delay tpdl drvh c load = 3 nf 20 ns drvh turn ? on propagation delay tpdh drvh c load = 3 nf 27 ns sw pull down resistance sw to pgnd 45 k
NCP81146 http://onsemi.com 5 table 4. electrical characteristics ( unless otherwise stated: ? 40 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst ? swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter units max. typ. min. test conditions high side driver (vcc = 5 v) drvh pull down resistance drvh to sw, bst ? sw = 0 v 45 k low side driver (vcc = 12 v) output impedance, sourcing current 2.0 3.0 output impedance, sinking current 0.7 1.5 drvl rise time tr drvl c load = 3 nf 16 35 ns drvl fall time tf drvl c load = 3 nf 11 20 ns drvl turn ? off propagation delay tpdl drvl c load = 3 nf 35 ns drvl turn ? on propagation delay tpdh drvl c load = 3 nf 8.0 30 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 45 k low side driver (vcc = 5 v) output impedance, sourcing current 2.5 output impedance, sinking current 1.0 drvl rise time tr drvl c load = 3 nf 30 ns drvl fall time tf drvl c load = 3 nf 22 ns drvl turn ? off propagation delay tpdl drvl c load = 3 nf 27 ns drvl turn ? on propagation delay tpdh drvl c load = 3 nf 12 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 45 k en input input voltage high 2.0 v input voltage low 1.0 v hysteresis 500 mv normal mode bias current ? 1 1 a enable pin sink current 4 30 ma propagation delay time 20 40 ns sw node sw node leakage current 20 a zero cross detect ion thres hold voltage sw to ? 20 mv, ramp slowly until bg goes off (start in dcm mode) (note 3) ? 6 mv table 5. decoder truth table pwm input zcd drvl drvh pwm high zcd reset low high pwm mid positive current through the inductor high low pwm mid zero current through the inductor low low pwm low zcd reset high low 3. guaranteed by design; not production tested.
NCP81146 http://onsemi.com 6 figure 4. figure 5. timing diagram pwm drvh ? sw drvl il 1v 1v
NCP81146 http://onsemi.com 7 applications information the NCP81146 gate driver is a single phase mosfet driver designed for driving n ? channel mosfets in a synchronous buck converter topology. the NCP81146 is designed to work with on semiconductor?s ncp6131 multi ? phase controller. this gate driver is optimized for desktop applications. undervoltage lockout the drvh and drvl are held low until v cc reaches 4.5 v during startup. the pwm signals will control the gate status when v cc threshold is exceeded. if v cc decreases to 250 mv below the threshold, the output gate will be forced low until input voltage v cc rises above the startup threshold. power ? on reset power ? on reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. when the initial soft ? start voltage is higher than 2.75 v, the gate driver will monitor the switching node sw pin. if sw pin high than 2.25 v, bottom gate will be force to high for discharge the output capacitor. the fault mode will be latch and en pin will force to be low, unless the driver is recycle. when input voltage is higher than 4.5 v, and en goes high, the gate driver will normal operation, top gate driver drvh and bottom gate driver will follow the pwm signal decode to a status. bi ? directional en signal fault modes such as power ? on reset and undervoltage lockout will de ? assert the en pin, which will pull down the dron pin of controller as well. thus the controller will be shut down consequently. pwm input and zero cross detect (zcd) the pwm input, along with en and zcd, control the state of drvh and drvl. when pwm is set high, drvh will be set high after the adaptive non ? overlap delay. when pwm is set low, drvl will be set high after the adaptive non ? overlap delay. when the pwm is set to the mid state, drvh will be set low, and after the adaptive non ? overlap delay, drvl will be set high. drvl remains high during the zcd blanking time. when the timer is expired, the sw pin will be monitored for zero cross detection. after the detection, the drvl will be set low. adaptive nonoverlap the nonoverlap dead time control is used to avoid the shoot through damage the power mosfets. when the pwm signal pull high, drvl will go low after a propagation delay, the controller will monitors the switching node (swn) pin voltage and the gate voltage of the mosfet to know the status of the mosfet. when the low side mosfet status is off an internal timer will delay turn on of the high?side mosfet. when the pwm pull low, gate drvh will go low after the propagation delay (tpd drvh ). the time to turn off the high side mosfet is depending on the total gate charge of the high ? side mosfet. a timer will be triggered once the high side mosfet is turn off to delay the turn on the low ? side mosfet. low ? side driver timeout in normal operation, the drvh signal tracks the pwm signal and turns off the q1 high ? side switch with a few 10 ns delay (t pdldrvh ) following the falling edge of the input signal. when q1is turned off, drvl is allowed to go high, q2 turns on, and the sw node voltage collapses to zero. but in a fault condition such as a high ? side q1 switch drain ? source short circuit, the sw node cannot fall to zero, even when drvh goes low . this driver has a timer circuit to address this scenario. every time the pwm goes low, a drvl on ? time delay timer is triggered. if the sw node voltage does not trigger a low ? side turn ? on, the drvl on ? time delay circuit does it instead, when it times out with t sw(to) delay. if q1 is still turned on, that is, its drain is shorted to the source, q2 turns on and creates a direct short circuit across the vdcin voltage rail. the crowbar action causes the fuse in the vdcin current path to open. the opening of the fuse saves the load (cpu) from potential damage that the high ? side switch short circuit could have caused. layout guidelines layout for dc ? dc converter is very important. the bootstrap and v cc bypass capacitors should be placed as close as to the driver ic. connect gnd pin to local ground plane. the ground plane can provide a good return path for gate drives and reduce the ground noise. the thermal slug should be tied to the ground plane for good heat dissipation. to minimize the ground loop for low side mosfet, the driver gnd pin should be close to the low ? side mosfet source pin. the gate drive trace should be routed to minimize the length, the minimum width is 20 mils. gate driver power loss calculation the gate driver power loss consists of the gate drive loss and quiescent power loss. the equation below can be used to calculate the power dissipation of the gate driver. where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet. p drv [ f sw 2 n n mf q gmf n sf q gsf i cc ] v c c also shown is the standby dissipation factor (i cc ? v cc ) of the driver.
NCP81146 http://onsemi.com 8 package dimensions dfn8 2x2 case 506aa issue e ?? ?? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l (a3) d2 e2 c c 0.15 c 0.10 c 0.08 note 4 a1 seating plane e/2 e 8x k note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k l 0.25 0.35 1 4 8 5 l1 detail a l optional constructions l ??? 0.10 0.30 ref *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.50 8x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended 0.90 1.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCP81146/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca sales representative
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